Description

• Physical Design of blocks (from synthesis to GDS) and handle complex block implementation individually.
• PPA optimization.
• Develop and validate high performance and/or low- power clock network guidelines.
• Perform block-level place and route and close the design to meet timing, area and power constraints.
• Drive the logic equivalency RTL2Synthesis and Synthesis2APR netlist.
• Generate and implement ECOs to fix timing, noise and EM-IR violations.
• Run physical design verification flow at block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct-by-construction designs.
• Assist in P&R flow development and/or refinement for chip integration.
• Write scripts in TCL/Perl/Python to achieve productivity enhancements through automation.

• BSEE or MSEE with at least 6+ years of physical design experience on high complexity SoC designs using 7 nm or lower.
• Strong understanding of all aspects of physical construction, integration, sign-off and physical verification
• Good understanding of placement, clocking & routing strategies, challenges and their mitigation/solutions.
• To be able to work with logic/rtl design team for timing fixes.
• Solid understanding of extraction and STA methodology and tools description.
• Power user of industry standard physical design and signoff tools.
• Deep understanding of scripting languages such as Perl/Tcl/Python

• Hands-on SoC floorplanning and expertise in analog, ESD etc. placement and related rules.
• SoC PV clean-up at floorplan stage