Description

• Physical Design of blocks (from synthesis to GDS) and handle complex block implementation individually but not limited to DDR.
• Handle all aspects of Physical Design as needed from DDR PD perspective which may include bump planning, co-ordination with SoC floorplan but not limited to these.
• Own design of multiple blocks as a technical lead as needed.
• PPA optimization.
• Develop and validate high performance and/or low- power clock network guidelines.
• Perform block-level place and route and close the design to meet timing, area and power constraints.
• Drive the logic equivalency RTL2Synthesis and Synthesis2APR netlist.
• Generate and implement ECOs to fix timing, noise and EM-IR violations.
• Run physical design verification flow at block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing P&R flows and physical design methodologies for correct-by-construction designs.
• Assist in flow development and/or refinement for chip integration.
• Write scripts in TCL/Perl/Python to achieve productivity enhancements through automation.

• BE/BTECH or ME/MTECH 12+ years of experience in physical design using 7 nm or lower.
• DDR PD expertise is a must, exerptise with 3DIC or PCIE-high speed interface is also good.
• Timing Signoff experience with SNPS or industry standard tools
• PDN: IR signoff and Physical verification knowledge
• Automation skills python/Perl/TCL
• RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff
• Proficiency in automation to drive improvements in PPA.
• Experience working on multiple technology nodes in advanced processes.
• Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
• Familiarity with ASIC design flows and physical design methodologies.
• Design level knowledge to optimize the implementation for PPPA.